Department of Mechanical and Aerospace EngineeringNEWS & EVENTS
MECH6090M PG SEMINAR

Heterogeneous Integration
John H Lau
ASM Pacific Technology
Date  :  03 Oct 2017 (Tue)
Time  :  3:00 p.m.
Venue  :  Room 2304, HKUST (2/F., Lift #17/18)

Abstract

Because of the drive of Moore’s law and compounded with the demands of mobile products such as smartphones and tablets, SoC (system-on-chip) has been very popular in the past 10+ years. SoC integrates ICs with different functions into a single chip for the system or subsystem. Unfortunately, the end of Moore’s law is fast approaching and it is more and more difficult and costly to reduce the feature size (to do the scaling) to make the SoC. Heterogeneous integration is against SoC. It has been a very “fancy” name in semiconductor packaging in the past few years. Heterogeneous integration use packaging technology to integrate the dissimilar chips with different functions into a system or subsystem instead of integrating all the functions into a single chip and go for finer feature size. For the next five years, we will see more of a higher level of heterogeneous integration, whether it is for performance, form factor, power consumption or cost. SiP (system-in-package) is similar to heterogeneous integration but with less density and gross pitch. In this lecture, the following topics will be presented. Emphasis is placed on the latest developments of these areas in the past three years. Their future trends will also be recommended.
 
SoC
  • Apple’s application processor (A9)
  • Apple’s application processor (A10)
SiP
  • Amkor’s SiP for automobiles
  • Apple Watch II (S2) assembled by ASE
Heterogeneous Integration with SoW (System-on-Wafer)
  • Leti’s SoW
  • ULCA’s Sow
Heterogeneous Integration with TSV-Interposers
  • TSMC/Xilinx’s CoWoS
  • AMD’s GPU with Hynix’s HBM and UMC’s TSV-interposer
  • Nvidia’s GPU with Samsung’s HMB2 and TSMC’s TSV-interposer
Heterogeneous Integration with TSV-less Interposer
  • Xilinx/SPIL’s TSV-less SLIT
  • SPIL/Xilinx’s TSV-less NTI
  • Amkor’s TSV-less SLIM
  • ASE’s TSV-less FOCoS
  • MediaTek’s TSV-less RDLs by FOWLP
  • Intel’s TSV-less EMIB
  • Intel/AMD’s TSV-less EMIB for CPU, GPU, and HBM
  • Intel’s Knight-Landing with Micron’s HMC on TSV-less Organic Interposer
  • Cisco/eSilicon’s TSV-less Organic Interposer
  • ITRI’s TSV-less TSH
  • Shinko’s TSV-less i-THOP


Bio

Dr. John Lau has been a Sr. Technical Advisor of ASM since July 2014. Prior to that, he was an ITRI Fellow of Industrial Technology Research Institute (Taiwan) for 4.5 years, a visiting professor at HKUST for 1 year, the Director of MMC Laboratory with IME Singapore for 2 years and a Senior Scientist/MTS at Hewlett-Packard/Agilent in California, US for more than 25 years. With more than 38 years of R&D and manufacturing experience, he has published more than 435 peer-reviewed papers, 30 issued and pending patents, and 18 textbooks on, e.g., Reliability of RoHS compliant 2D and 3D IC Interconnects (2011), TSV for 3D Integration, (2013), and 3D IC Integration and Packaging (2015). Dr. Lau is also a fellow of IEEE, ASME, and IMAPS.




Dr. John Lau